> Overview

> Hardware

> FPGA design

> Software

> Web interface

The NSApp interfaces to the boards. Each task is divided into Work Units that span a 6-character range (for instance, everything from Kz...... to Kz000000). Chips receive WUs on a first-come, first-serve basis, with 1 thread servicing each board.

The software currently has no user interface. This will be added as a TCP/IP based protocol that will allow tasks to be specified from an external system, for instance this web page.

First, boards are detected and initialized. Then, the hash map is compiled so that it can be loaded into the FPGAs. All WUs are created from the input parameters (text prefix and length) and placed into a "to-do" queue.

Then, per-board threads await WUs and assign them to chips; subsequently, results are collected from boards and checked against the hash list in software. Since the hardware matches only 32 first bits of each hash, the rest of a 160-bit SHA1 has to be verified by the NSApp.

Results are output to a text file that will be eventually split into one file per input hash and emailed to requesters.

You can find the current NSApp source here.